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Single-chip Type with Built-in FET Switching Regulator
High-efficiency Step-up Switching Regulator with Built-in Power MOSFET
BD8314NUV
No.09027EAT09
General Description ROHM's High-efficiency Step-up Switching Regulator Built-in Power MOSFET BD8314NUV generates step-up output including 8 V or 10 V from 4 batteries, batteries such as Li1cell or Li2cell etc. or a 5 V fixed power supply line. This IC allows easy production of small and a wide range of output current, and is equipped with an external coil/capacitor downsized by high frequency operation of 1.2 MHz, built-in 2.5 A rated 80 m Nch FET SW, and flexible phase compensation system on board. Features 1) Incorporates Nch FET capable of withstanding 2.5 A/14 V. 2) Incorporates phase compensation device between input and output of ERROR AMP. 3) Small coils and capacitors to be used by high frequency operation of 1.2 MHz 4) Input voltage 3.0 V - 12 V 5) Output current 600 mA (3.5 V - 10 V) at 10 V 600 mA (3.0 V - 8 V) at 8 V 6) Incorporates soft-start function. 7) Incorporates timer latch system short protecting function. VSON010V3030 8) As small as 3 mm, SON 10-pin package Application General portable equipment like DSC/DVC powered by 4 dry batteries or Li2cell Operating Conditions (Ta = 25C) Parameter Power supply voltage Output voltage Absolute Maximum Ratings Parameter Maximum applied power voltage Maximum input voltage Maximum input current Power dissipation Operating temperature range Storage temperature range Junction temperature Symbol VCC, LX SWOUT, INV Iinmax Pd Topr Tstg Tjmax Rating 14 14 2.5 700 -25 to +85 -55 to +150 +150 Unit V V A mW C C C Symbol VCC VOUT Voltage range 3.0 to 12 4.0 to 12 Unit V V
*1 When used at Ta = 25C or more installed on a 74.2 x 74.2 x 1.6t mm board, the rating is reduced by 5.6 mW/C. * These specifications are subject to change without advance notice for modifications and other reasons.
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1/15
2009.03 - Rev.A
BD8314NUV
Electrical Characteristics (Unless otherwise specified, Ta = 25 C, VCC = 7.4 V) Target Value Typical Maximum 2.4 100 1.2 5.0 1.00 0 8.8 85 50 80 0 400 600 2.6 200 1.3 5.35 1.01 50 12.2 93 100 150 1 11 0.3 700 1 900
Technical Note
Parameter
Symbol
Minimum 50 1.1 4.65 0.99 -50 5.3 77 -1 2.5 -0.3 250 -
Unit V mV MHz V V nA msec % m uA V V k uA uA
Conditions VREG monitor
[Low voltage input malfunction preventing circuit] Detection threshold voltage VUV Hysteresis range VUVhy [Oscillator] Oscillation frequency fosc [Regulator] Output voltage VREG [ERROR AMP] INV threshold voltage VINV Input bias current IINV Soft-start time Tss [PWM comparator] LX Max Duty Dmax1 [SWOUT] ON resistance RONSWOUT [Output] LX NMOS ON resistance RON LX leak current Ileak [STB] Operation VSTBH STB pin control voltage No-operation VSTBL STB pin pull-down resistance RSTB [Circuit current] Standby current VCC ISTB Circuit current at operation VCC Icc
Vcc=11.0V , VINV=5.5V
VINV=1.2V
Not designed to be resistant to radiation
Description of Pins
Pin No. 1 2 GND VCC VREG LX LX SWOUT 3 INV STB PGND PGND 45 67 8 9 10
Pin Name GND VCC VREG Lx PGND STB INV SWOUT
Function
Ground terminal
Control part power input terminal 5 V output terminal of regulator for internal circuit Coil connecting terminal Power transistor ground terminal ON/OFF terminal ERROR AMP input terminal
STBSW for split resistance
Fig.1 Pin layout
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2/15
2009.03 - Rev.A
BD8314NUV
Block Diagram
Technical Note
STB
VREG
VCC
STBY_IO VREG
OSC 1.2MHz
FB H
5V REG
Reference
VREF
UVLO
GND
SCP
OSCx16000 ount VREG
Lx
STOP
PWM CONTROL
PRE DRIVER
80m
PGND
+ + -
ERROR_AMP
VREF Soft Start
SWOUT
STB
50
INV
Fig.2 Block diagram
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3/15
2009.03 - Rev.A
BD8314NUV
Description of Blocks 1. VREF This block generates ERROR AMP reference voltage. The reference voltage is 1.0 V.
Technical Note
2. UVLO Circuit for preventing low voltage malfunction Prevents malfunction of the internal circuit at activation of the power supply voltage or at low power supply voltage. Monitors VREG pin voltage to turn off all output FET and DC/DC converter output when VREG voltage is lower than 2.4 V, and reset the timer latch of the internal SCP circuit and soft-start circuit. This threshold contains 100 mV hysteresis. 3. SCP Timer latch system short-circuit protection circuit When the INV pin is the set 1.0 V or lower voltage, the internal SCP circuit starts counting. The internal counter is in synch with OSC; the latch circuit activates after a lapse of 13.3 msec after the counter counts about 16000 oscillations and then, turn off DC/DC converter output. To reset the latch circuit, turn off the STB pin once. Then, turn it on again or turn on the power supply voltage again. OSC Circuit for oscillating sawtooth waves with an operation frequency fixed at 1.2 MHz ERROR AMP Error amplifier for detecting output signals and outputting PWM control signals The internal reference voltage is set at 1.0 V. A primary phase compensation device of 200 pF, 62 k is built in between the inverting input terminal and the output terminal of this ERROR AMP. PWM COMP Voltage-pulse width converter for controlling output voltage corresponding to input voltage Comparing the internal SLOPE waveform with the ERROR AMP output voltage, PWM COMP controls the pulse width to the output to the driver. Max Duty is set at 85%. SOFT START Circuit for preventing in-rush current at startup by bringing the output voltage of the DC/DC converter into a soft-start Soft-start time is in synch with the internal OSC, and the output voltage of the DC/DC converter reaches the set voltage after about 10000 oscillations . PRE DRIVER CMOS inverter circuit for driving the built-in Nch FET.
4.
5.
6.
7.
8.
9. STBY_IO Voltage applied on STB pin (8 pin) to control ON/OFF of IC Turned ON when a voltage of 2.5 V or higher is applied and turned OFF when the terminal is open or 0 V is applied. Incorporates approximately 400 k pull-down resistance. 10. Nch FET SW Built-in SW for switching the coil current of the DC/DC converter. Incorporates an 80 m NchFET SW capable of withstanding 14 V. Since the current rating of this FET is 2.5 A, it should be used within 2.5 A including the DC current and ripple current of the coil.
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4/15
2009.03 - Rev.A
BD8314NUV
Reference Data (Unless otherwise specified, Ta = 25C, VCC = 7.4 V)
Technical Note
1.02
1.02
5.3
5.2
1.01 1.01
INV THRESHOLD [V]
VREG VOLTAGE [V]
INV THRESHOLD [V]
5.1
1.00
1.00
5.0
4.9
0.99
0.99
4.8
0.98 -40 -20 0 20 40 60 80 100 120 TEMPERATURE []
0.98 0 2 4 6 8 10 12 14
4.7 -40 0 40 80 120
VCC [V]
TEMPERATURE []
Fig.3. INV threshold temperature property
Fig.4. INV threshold power supply property
Fig.5. VREG output temperature property
8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14
1.4
1.4
1.3
1.3
FREQUENCY [MHz]
1.2
1.1
1.0
FREQUENCY [ MHz ]
VREG[V]
1.2
1.1
1.0
-40
0
40
80
120
3
6
9
12
15
VCC [V]
TEMPERATURE []
VCC [V]
Fig.6. VREG output power supply property
Fig.7.
fosc
temperature
Fig.8.
fosc
voltage
3.5 UVLO THRESHOLD VOLTAGE [ ] 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 -40 -20 0 25 50 85 100 120 TEMPARATURE []
UVLO detection UVLO release
0.25
160 140 120
120
Hysteresis Voltage Vhys[V] Vhys [V]
ID=500mA
100
ID=500mA
0.20
ON RESISTANCE [ m ]
ON RESISTANCE [ m]
80
0.15
100 80 60 40 20
Hysteresis width
0.10
60
40
0.05
20
0.00
0 -40 0 40 80 120
0 3 6 9 12 15
TEMPARATURE []
VCC [V]
Fig.9. UVLO threshold temperature property
Fig.10. Nch FET ON resistance temperature
Fig.11. Nch FET ON resistance power supply
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5/15
2009.03 - Rev.A
BD8314NUV
Technical Note
2.5
100
100
SWOUT ON Resistance [ ]
80
ID=1mA
SWOUT ON Resistance [ ]
80
ID=1mA
STB Voltage [V]
2.0
ON
60
60
40
40
1.5
20
20
OFF
1.0 -50 0 50 100 150
0 -40 0 40 80 120 0 3 6 9 12 15
VCC [V]
TEMPARATURE []
VCC [V]
Fig.12. STB threshold temperature property
Fig.13. SWOUT ON resistance temperature property
Fig.14. SWOUT ON resistance power supply property
95
95
2.5
90
90
Lx Max Duty [ % ]
2.0
Lx Max Duty [%]
85
85
80
80
75
-40 0 40 80 120
75 3 6 9 12 15
STB Voltage [V]
1.5
1.0 -50 0 50 100 150
TEMPARATURE []
VCC [V]
TEMPARATURE []
Fig.15. Lx Max duty temperature property
Fig.16. Lx Max duty power supply property
Fig.17. Circuit current temperature property
1000
800
600
ICC [uA]
400
200
0 0 2 4 6 8 10 12 14
VCC [V]
Fig.18. Circuit current power supply property
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6/15
2009.03 - Rev.A
BD8314NUV
Example of Application Input: 3.0 to 10 V, output: 10 V / 500 mA
Technical Note
RSX201L-30 ROHM 10V/500mA
22F GRM32EB31C226KE16Murata 4.7H DE3518ETOKO
6
PGND
Lx
5
VBAT=2.54.5V
10p
7
ON/OFF
PGND STB
Lx
4 3 2
1F GRM188B11A105KA61Murata
10F GRM31CB31E106KA75LMurata
200k
8 9
VREG VCC
10k
100k 22k
INV
1F GRM21BB11C105KA01Murata
3.35.0V
10
SWOUT
GND
1
Fig.19 Reference application diagram
Reference Application Data 1
100 100 100
VCC=10V
80 80
VCC=6.0V
EFFICIENCY [%]
80
VCC=4.0V
EFFICIENCY [%]
EFFICIENCY [%]
60
VCC=8.4V
VCC=7.4V
60
60
VCC=4.8V
40
VCC=3.5V
40
40
20
20
20
0 1 10 100 1000 10000
0 1 10 100 1000 10000
0 1 10 100 1000 10000
OUTPUT CURRENT [mA]
OUTPUT CURRENT [mA]
OUTPUT CURRENT [mA]
Fig.20 Power conversion
Fig.21 Power conversion
Fig.22 Power conversion
15 14 13
10.5 10.4
10.5 10.4
Io=100mA
OUTPUT VOLTAGE [V]
10.3 10.2
VCC=10V
OUTPUT VOLTAGE [V]
10.3 10.2 10.1 10.0 9.9 9.8
OUTPUT VOLTAGE [V]
12 11 10 9 8 7 6 5 0 2 4 6 8 10 12
VCC=8.4V
10.1 10.0 9.9 9.8 9.7 9.6 9.5 1 10 100 1000 10000
VCC=4.8V
Io=500mA
VCC=7.4V VCC=6.0V
VCC=4.0V VCC=3.5V
9.7 9.6 9.5 1 10 100 1000 10000
INPUT VOLTAGE [V]
OUTPUT CURRENT [mA]
OUTPUT CURRENT [mA]
Fig.23 Line regulation
Fig.24 Load regulation 1
Fig.25 Load regulation 2
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7/15
2009.03 - Rev.A
BD8314NUV
Reference Application Data 2 (VCC = 3.0 V, 6.0 V, 8.4 V, VOUT = 10 V)
Technical Note
60 40
180 120
60
180
60 40 20
Phase [deg]
180
Phase
Phase
40 20 Gain [dB] 0 -20 -40 -60 120 60
120 60 0 Phase [deg]
Phase [deg]
Phase
20 Gain [dB] 0 -20 -40 -60 60 Phase [deg] 0
Gain [dB]
Gain
0 -60 -120 -180 100k 1M 100000 1000000
0
Gain
Gain
-60 -120 -180 100k 1M 100000 1000000
-20 -40 -60
100 100 1k 1000 10k 10000
-60 -120 -180 100k 1M 100000 1000000
100 100
1k 1000
10k 10000
100 100
1k 1000
10k 10000
[Hz] Frequency [Hz]
Fig.26 Frequency response property 1 (VCC = 3.0 V, Io = 200 mA)
100 60 40 Phase 20 Gain [dB] 0 -20 -40 -60 100 100 1k 1000 10k 10000 100k 100000 [Hz] Frequency [Hz] 60 Phase [deg] 0 -60 -120 -180 1M 1000000 1k 10k 100k 1M 180 120
[Hz] Frequency [Hz]
Frequency [Hz] [Hz]
Fig.27 Frequency response property 2 (VCC = 6.0 V, Io = 200 mA)
60 180
Fig.28 Frequency response property 3 (VCC = 8.4 V, Io = 200 mA)
60 180
40 20 Gain [dB]
Phase
120 60 Phase [deg]
40 20 Gain [dB]
Phase
120 60
0
0
0 Gain -20 -40
0
Gain
-20 -40 -60 -120
Gain
-60 -120
-60
100 100
1k 1000
10k 10000
100k 100000
-180 1M 1000000
-60 100 100 1k 1000 10k 10000 100k 100000
-180 1M 1000000
Frequency[Hz] [Hz]
Frequency [Hz] [Hz]
Fig.29 Frequency response property 4 (VCC = 3.0 V, Io = 500 mA)
Fig.30 Frequency response property 5 (VCC = 6.0 V, Io = 500 mA)
Fig.31 Frequency response property 6 (VCC = 8.4 V, Io = 500 mA)
Reference Board Pattern
VOUT
GND
Lx
VBAT
- The radiation plate on the rear should be a GND flat surface of low impedance in common with the PGND flat surface. - It is recommended to install a GND pin in another system as shown in the drawing without connecting it directly to this PGND
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8/15
2009.03 - Rev.A
BD8314NUV
Technical Note
Limits of the lowest power supply voltage to start up When using configuration of inputting VCC voltage from output voltage of DC/DC converter, the input voltage as power supply for the IC drops by Vf voltage of external Diode. The worst condition is shown as below. VCC terminal voltage Vf voltage of external diode the worst voltage of UVLO reset voltage(=2.8V)
Please judge this IC is useable or not considering needed start up voltage and load current.
3.2
VOUT=10V, typ
3.0
2.8
-35
VBAT [ V ]
2.6
2.4
85
25
2.2 0.1 1.0 10.0 100.0
Io [mA]
Fig.32 start up voltage Vs load current
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9/15
2009.03 - Rev.A
BD8314NUV
Selection of Part for Applications
Technical Note
(1) Inductor A shielded inductor that satisfies the current rating (current value, Ipecac as shown in the drawing below) and has a low DCR (direct resistance component) is recommended. Inductor values affect inductor ripple current, which will cause output ripple. Ripple current can be reduced as the coil L value becomes larger and the IL switching frequency becomes higher. Ipeak =Iout x(Vout/VIN) / IL/2 [A] (1)
Fig.33 Inductor current
IL=
Vin L
x
Vout -Vin Vout
x
1 f
[A]
(2)
(: Efficiency, IL: Output ripple current, f: Switching frequency) As a guide, inductor ripple current should be set at about 20 to 50% of the maximum input current. * Current over the coil rating flowing in the coil brings the coil into magnetic saturation, which may lead to lower efficiency or output oscillation. Select an inductor with an adequate margin so that the peak current does not exceed the rated current of the coil.
(2) Output capacitor A ceramic capacitor with low ESR is recommended for output in order to reduce output ripple. There must be an adequate margin between the maximum rating and output voltage of the capacitor, taking the DC bias property into consideration. Output ripple voltage is obtained by the following equation. Vpp=Iout x Vout-Vin fxCoxVout + Iout x RESR [V] ... (3)
Setting must be performed so that output ripple is within the allowable ripple voltage.
(3) Output voltage setting The internal reference voltage of the ERROR AMP is 1.0 V. Output voltage is obtained by Equation (4) of Fig. 33, but it should be designed taking about 50 , an error of NMOS ON resistance of SWOUT into consideration.
VOUT
R1 INV R2
ERROR AMP
(R1+R2)
Vo=
R2
x1.0 [V] (4)
VREF 1.0V SWOUT STB
Fig.34 Setting of voltage feedback resistance
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10/15
2009.03 - Rev.A
BD8314NUV
(4) DC/DC converter frequency response adjustment system
Technical Note
Condition for stable application The condition for feedback system stability under negative feedback is that the phase delay is 135 or less when gain is 1 (0 dB). Since DC/DC converter application is sampled according to the switching frequency, the bandwidth GBW of the whole system (frequency at which gain is 0 dB) must be controlled to be equal to or lower than 1/10 of the switching frequency. In summary, the conditions necessary for the DC/DC converter are: - Phase delay must be 135or lower when gain is 1 (0 dB). - Bandwidth GBW (frequency when gain is 0 dB) must be equal to or lower than 1/10 of the switching frequency. To satisfy above two items, R1, R2, R3, DS and RS in Fig. 34 should be set as follows.
[1] R1, R2, R3 BD8314NUV incorporates phase compensation devices of R4=62 k and C2=200pF. These C2 and R1, R2, and R3 values decide the prim ary pole that determines the bandwidth of DC/DC converter. Primary pole point frequency 1 R1R2 2 Ax( +R3)xC2 R1+R2
VOUT R1 Cs Rs FB R2 R3 Inside of IC R4 C2
fp=
**************** (1) Fig.35 Example of phase compensation setting A: ERROR AMP Gain About 100dB = 105 B: Oscillator amplification = 0.5 VIN: Input voltage VOUT: Output voltage
DC/DC converter DC Gain
1 B
DC Gain =Ax
x
VOUT VOUT-VIN
****************(2)
By Equations (1) and (2), the frequency fsw of point 0 dB under limitation of the bandwidth of the DC gain at the primary pole point is as shown below. 1 fSW = fpxDC Gain =
(R1R2) 2C2x( +R3 ) (R1+R2)
x
1 B
x
VOUT VOUT-VIN
****************(3)
It is recommended that fsw should be approx.10 kHz. When load response is difficult, it may be set at approx. 20 kHz. By this setting, R1 and R2, which determine the voltage value, will be in the order of several hundred k. Therefore, if an appropriate resistance value is not available and routing may cause noise, the use of R3 enables easy setting.
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11/15
2009.03 - Rev.A
BD8314NUV
Technical Note
[2] Cs and Rs setting In the step-up DC/DC converter, the secondary pole point is caused by the coil and capacitor as expressed by the following equation. 1D 2(LC) **************** (4)
fLC=
D:
ON Duty = ( VOUT - VIN ) / VOUT
This secondary pole causes a phase rotation of 180. To secure the stability of the system, put zero points in 2 places to perform compensation. 1 Zero point by built-in CR fZ1= 2R4C2 Zero point by Cs fZ1= 1 2(R1+R3)CS **************** (6) **************** (5) = 13kHz
Setting CS2 to be half to 2 times a frequency as large as fLC provides an appropriate phase margin. It is desirable to set Rs at about 1/20 of (R1+R3) to cancel any phase boosting at high frequencies. Those pole points are summarized in the figure below. The actual frequency property is different from the ideal calculation because of part constants. If possible, check the phase margin with a frequency analyzer or network analyzer, etc.. Otherwise, check for the presence or absence of ringing by load response waveform and also check for the presence or absence of oscillation under a load of an adequate margin.
(5) (6)
(3) (4)
Fig. 36 Example of DC/DC converter frequency property (Measured with FRA5097 by NF Corporation)
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12/15
2009.03 - Rev.A
BD8314NUV
I/O Equivalence Circuit
Technical Note
FB
INV
VCC VREG
VREG
VREG
FB
INV
VREG
SWOUT
VCC
VCC
VCC
VREG
SWOUT
STB
VCC VCC
Lx, PGND
Lx
STB
PGND
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13/15
2009.03 - Rev.A
BD8314NUV
Precautions for Use
Technical Note
1) Absolute Maximum Rating We dedicate much attention to the quality control of these products, however the possibility of deterioration or destruction exists if the impressed voltage, operating temperature range, etc., exceed the absolute maximum ratings. In addition, it is impossible to predict all destructive situations such as short-circuit modes, open circuit modes, etc. If a special mode exceeding the absolute maximum rating is expected, please review matters and provide physical safety means such as fuses, etc. 2) GND Potential Keep the potential of the GND pin below the minimum potential at all times. 3) Thermal Design Work out the thermal design with sufficient margin taking power dissipation (Pd) in the actual operation condition into account. 4) Short Circuit between Pins and Incorrect Mounting Attention to IC direction or displacement is required when installing the IC on a PCB. If the IC is installed in the wrong way, it may break. Also, the threat of destruction from short-circuits exists if foreign matter invades between outputs or the output and GND of the power supply. 5) Operation under Strong Electromagnetic Field Be careful of possible malfunctions under strong electromagnetic fields. 6) Common Impedance When providing a power supply and GND wirings, show sufficient consideration for lowering common impedance and reducing ripple (i.e., using thick short wiring, cutting ripple down by LC, etc.) as much as you can. 7) Thermal Protection Circuit (TSD Circuit) This IC contains a thermal protection circuit (TSD circuit). The TSD circuit serves to shut off the IC from thermal runaway and does not aim to protect or assure operation of the IC itself. Therefore, do not use the TSD circuit for continuous use or operation after the circuit has tripped. 8) Rush Current at the Time of Power Activation Be careful of the power supply coupling capacity and the width of the power supply and GND pattern wiring and routing since rush current flows instantaneously at the time of power activation in the case of CMOS IC or ICs with multiple power supplies.
9) IC Terminal Input
This is a monolithic IC and has P+ isolation and a P substrate for element isolation between each element. P-N junctions are formed and various parasitic elements are configured using these P layers and N layers of the individual elements. For example, if a resistor and transistor are connected to a terminal as shown on Fig.36: The P-N junction operates as a parasitic diode when GND > (Terminal A) in the case of a resistor or when GND > (Pin B) in the case of a transistor (NPN) Also, a parasitic NPN transistor operates using the N layer of another element adjacent to the previous diode in the case of a transistor (NPN) when GND > (Pin B). The parasitic element consequently rises under the potential relationship because of the IC's structure. The parasitic element pulls interference that could cause malfunctions or destruction out of the circuit. Therefore, use caution to avoid the operation of parasitic elements caused by applying voltage to an input terminal lower than the GND (P board), etc.
Resistor (Pin A) (Pin B)
Transistor (NPN) B C

E GND
N P N N P Substrate P P N P N P Substrate Parasitic Element Parasitic Element GND P P N
Parasitic Element GND
Fig.37 Example of simple structure of Bipolar IC
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14/15
2009.03 - Rev.A

(Pin A)
BD8314NUV
Ordering part number
Technical Note
B
D
8
Part No.
3
1
4
N
U
V
-
E
2
Part No.
Package NUV: VSON010V3030
Packaging and forming specification E2: Embossed tape and reel (VSON010V3030)
VSON010V3030
3.0 0.1

3.0 0.1
Tape Quantity Direction of feed
Embossed carrier tape 3000pcs E2
(The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand)
1PIN MARK
1.0MAX
S
0.08 S
2.0 0.1 C0.25 0.5
0.02 - 0.02 (0.22)
+ 0.03
1234
1234
1234
1234
1234
1234
1
5
1.2 0.1
0.4 0.1
10
0.5
6
0.25 + 0.05 - 0.04
Reel
1Pin
Direction of feed
(Unit:mm)
When you order , please order in times the amount of package quantity.
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15/15
2009.03 - Rev.A
Notice
Notes
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